Designing an Easily Modified LED Sequencer With No Processor Intervention

As LED technology continues to be used in more and more applications, it is also becoming quite common for developers to seek ways to minimize cost and design complexity by implementing an LED or other device sequencer on a system-on-chip(SOC) platform. SOC devices integrate the MCU capacity and various digital peripherals required to support a complete LED subsystem using a single chip. This article describes a simple 8 LED sequencer design based on the latest SOC technology.

However, the highlight in this design is that there is no interaction from the device's microprocessor. Instead of using the traditional passive digital peripherals with MCU processor intervention, this design is entirely based on the intelligently distributed processing functions in the SOC digital system. This frees the central CPU from managing the sequencer,eliminating any drain on horsepower and improving design efficiency.

This design approach can also be easily expanded to include timers, various lengths and patterns of sequence, and devices other than LEDs that are required to be powered up or down in a particular manner. Additional features were added to the design for demonstration purposes:

-terminal count out for a 7-bit counter (TC)
-direction output indicating whether the device is powering up or down
-8-bit output for the sequenced devices
-clock input for the Verilog state machine
-bus-clock for one 8-bit ALU (bit-slice) processor.

Data Path Configuration

The system on chip (SOC) technology revives bit-slice in a programmable fashion to serve the purpose of offloading the main CPU by intelligently assigning processing tasks to other on-chip programmable hardware. With such an approach, it is possible to develop a standard state machine. The difference is that normally arithmetic functions consume a large number of logic gates. This is no longer a concern because these functions are implemented in the standard ALU contained in the data path logic and/or controlled by the PLD-based state machine.

This design runs independently of the main CPU. The primary application can control the sequencer through an API which modifies execution parameters and, once the sequencer is initiated, the CPU is no longer required. Additionally, this type of implementation is inherently efficient, utilizing fewer transistors than methods using the CPU, resulting in better overall system power consumption and more available overhead for other advanced features.


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